1. Field of the Invention
The present invention relates in general to a memory error correction technique, and pertains, more particularly, to a technique for correcting correctable errors by recycling data that has been corrected by the memory error correction logic back into memory in order to clean up memory errors and, in particular, alpha particle (soft) failures.
2. Background Discussion
When a correctable error (CE) occurs in a memory, and, in particular, in association with dynamic random access memories (DRAMs), it is desirable to send the corrected data back into the memory to correct the failure, so that the probability of an uncorrectable error (UE) occurring is reduced. This involves the correcting of the correctable error by the error correcting code hardware, and, in addition, providing the corrected copy to the requesting processor and writing the corrected data back into the memory location from which it was read. This serves the purpose of "cleaning up" the error if it was a soft (alpha particle) error.
In one previous system, the memory controller accomplished this by placing the corrected data into a reserved location in the write buffer and setting the write pending bit. This causes the memory controller to treat this location in the write buffer as data that is to be written back into the memory DRAMs.
Present, larger capacity memory systems are different from previous memory systems in that while previous memories performed read or write on a maximum of 64 bits (78 bits including the error correcting code), present memory systems deal with as many as eight times this much information (eight double words or 512 bits or, alternatively, 576 bits with the error correcting code). Thus, due to this increased hardware requirement, the present storage control unit does not contain a write buffer in the traditional sense. Only addresses are buffered at the storage control unit and there is no provision for buffering groups of 576 bits. Rather, data is "staged" in a fetch pipeline. A "fetch pipeline" is a logic arrangement that holds data in a fetch data path while waiting for the system bus.
Because of the short cycle time of modern machines, and because of the many functions that need to be performed in the memory subsystem on fetch data, a fetch pipeline which operates like a CPU pipeline is implemented in order to hold the eight double words of fetch data on a read operation while the storage control unit is waiting to be granted use of the system bus (SYSBUS). Clearly, with this type of architecture, the previous method of recycling data employing a write buffer on a correctable error is not usable.
Accordingly, it is an object of the present invention to provide an improved system for memory error correction and, in particular, for correction of alpha particle type (soft) memory failures.
Another object of the present invention is to provide a memory error correction system for use in a system wherein the various processors employ writeback caches.